This invention is in the field of integrated circuit manufacturing, and is more specifically directed to the formation of metal conductors in modern integrated circuits.
In the field of integrated circuit manufacturing, a fundamental goal to design and manufacture integrated circuits to be as small as possible. As is well known in this art, the manufacturing cost of an integrated circuit corresponds strongly to the wafer area occupied by each integrated circuit die or chip. This is because the chip area correlates directly to the number of possible integrated circuits per manufactured wafer, and because the theoretical yield, for a given manufacturing defect density, increases as chip area decreases. In addition, the smaller feature sizes that result in decreasing chip area also provide improved device performance and increased functionality per unit area.
An important advance that has reduced the necessary chip area for modern integrated circuits is the technology for forming multiple levels of metal conductors. Increases in the number of available metal levels has provided dramatic reduction in chip area and in device and functionality density.
Of course, the implementation of multiple metal levels presents many challenges and tradeoffs. The cross-sectional area of each metal conductor is preferably minimized, especially in the lower levels, to permit overlying levels to make vertical connections, or contacts, to lower metal levels and to the underlying active devices. These narrower-pitch metal lines require high resolution photolithography. In addition, current density increases as the cross-sectional area of the conductors decrease, which increases the vulnerability of the finished conductors to electromigration. It is also desirable to make the dielectric insulating layers between adjacent metal levels as thin as possible, to facilitate the making of contacts from upper metal levels to underlying metal levels and active devices. These factors affect the selection of materials and fabrication methods for modern integrated circuit metallization.
Copper has become a popular metallization material in modern integrated circuits, replacing aluminum metallization in many instances. Copper is significantly more conductive than aluminum, and is also less vulnerable to electromigration failure than is aluminum. Damascene processes are often used to form multiple levels of copper conductors. In general, damascene processes refer to the inlaying of copper (or another metal) into grooves or trenches that are etched into an insulator to define the conductor lines. In contrast, traditional metallization is formed by the depositing of a film of metal over insulating films on the wafer surface, followed by the patterned etching of the metal film to define the conductors.
In general, dual damascene copper metal processes refer to metallization systems in which the deposited metal fills both trenches and vias in the etched insulator layer. Vias correspond to the locations at which the copper metal will make contact to an underlying feature, and as such vias are etched completely through the insulator layer. Trenches correspond to the locations of copper conductor runs, and as such trenches only partially extend into the insulator layer. Some processes are referred to as “trench first”, in which case the trenches are etched into the insulator before the vias are etched, while other processes are referred to as “via first”, because the vias are defined prior to trench etch. In either case, copper metal is deposited, typically by electrochemical deposition (e.g., electroplating), over the surface of the wafer and into the trenches and vias. In some processes (i.e., single damascene processes), a conductive plug of tungsten or polysilicon is formed into the vias before copper deposition. Chemical-mechanical polishing (CMP) is then performed to remove excess copper from the surface of the insulator, leaving the copper conductor inlaid within the trenches and vias. An insulator layer is then deposited over the structure, to insulate the newly-formed copper conductors from conductors in the next metal level.
In conventional dual damascene processing, trenches are coincident with vias, so that the single deposition of metal both forms the conductors and contacts a conductor in a previous, or lower, level. Because the exposures of the trench and via patterns are separate and independent from one another, in either the trench-first or via-first processes, misalignment of the trench pattern relative to the via pattern can often occur. The risk and extent of this misalignment is heightened for those levels in which the vias are being formed to the process limits, in order to attain maximum device density.
FIGS. 1a and 1b illustrate a conventional dual damascene process, and the effects of misalignment between trenches and vias. This process is similar to that described in U.S. Pat. No. 6,410,426, assigned to Texas Instruments Incorporated and incorporated herein by this reference. In this example, lower level conductor 2 is a metal or other conductive structure disposed within insulator film 1, and overlying active structures (not shown) in the device. According to this example, an overlying copper metallization element (not shown), formed according to a dual damascene process and thus disposed in a trench in insulating film 4, is to make connection to conductor 2 through a via that is formed through insulating film 4. Etch stop layer 3 is disposed at the surface of insulating film 1 and conductor 2. Insulating film 4, for example a low dielectric constant insulator, is disposed over etch stop layer 3, and is capped by cap layer 5, which is silicon carbide, tantalum nitride or another similar material for protecting insulating film 4 from the harsh etches used to form vias and trenches there through.
As shown in FIG. 1a, via V has been etched through insulating film 4, at a location defined by photolithography in the conventional manner. This via V extends to etch stop layer 3, which is resistant to etching by the reagent used to etch insulating film 4. At the state shown in FIG. 1a, photoresist pattern 8, with the assistance of bottom anti-reflective coating layer 6, has been photolithographically patterned to define the location of trench opening T, overlying the location of via V so that the conductor to be formed in the eventual trench contacts underlying conductor 2 through via V. However, as shown in FIG. 1a, the pattern of trench opening T is misaligned relative to via V, with photoresist 8 overlapping into via V. If trench opening T through photoresist 8 were perfectly aligned to via V, trench opening T would be centered and symmetric about via V. The misalignment of via V and trench opening T through photoresist 8 is shown in plan view in FIG. 1b. In addition, whether misaligned or not, BARC filament 7 will be present at the bottom of via V, as BARC layer 6 is dispensed after via formation. BARC filament 7 protects etch stop layer 3, at the bottom of via V, during the etching of the trench into insulating film 4.
Several manufacturing problems are endemic to conventional processes of this type. As evident from FIG. 1a and as mentioned above, BARC filament 7 is disposed within via V. Because of the depth of via V, the full extent of which has been formed through insulating film 4 at this point in the process, the top surface of BARC filament 7 will be some distance below the level of BARC layer 6 over insulating film 4 and cap dielectric 5. Considering today's high resolution photolithography processes and equipment, and the very short wavelengths used in this photo-exposure, it is believed, in connection with this invention, that the photolithography of trench opening T is made quite difficult by this differential height of BARC filament 7 relative to BARC layer 6. Because BARC layer 6 is spun-on, it thins at the edges of via V, resulting in non-optimal thickness and thus degraded anti-reflective properties at the edges of via V. This in turn reduces the fidelity of the photoresist pattern at trench location T. In addition, the depth of vias V exacerbates the natural thinning of photoresist 8 at locations where the via density is high; if photoresist 8 thins too much, it may not survive the trench etch process. For these reasons, it is contemplated that the proper exposure of photoresist 8 at the location of trench opening will be compromised in this conventional process, especially in the manufacture of modern high performance integrated circuits with small feature sizes and high via densities. As such, many modern via-first damascene processes, similar to that shown in FIGS. 1a and 1b, avoid the use of BARC layer 6 to avoid this very problem. This comes at a cost of suboptimal photolithographic results relative to that which can be achieved through the use of a BARC layer, resulting from reflection fringes, standing wave effects, and the like caused by reflection of the exposing light from the surface of cap layer 5 and etch stop layer 3.
By way of further background, other conventional dual damascene trench-via processes use an intermediate etch stop layer to define the depth of the trench in a trench-via dual damascene process. An example of such a process is described in U.S. Pat. No. 6,054,384. It has been observed, in connection with this invention, that misalignment of the trench pattern relative to the underlying via pattern in these conventional processes not only causes difficulty with the photolithography of the trench pattern, but also reduces the width of the via itself. Reduction in via width can result in poor conductivity between metal levels, and in extreme cases can result in voids or opens in the metal deposited into the via.
FIGS. 2a through 2d illustrate this reduction in via width, due to such misalignment in a conventional dual damascene process. Structure 10 may be an underlying conductor, such as a lower level copper conductor disposed in a trench. In this example, masking layer 11 (e.g., a silicon nitride) is disposed over structure 10, and insulating layer 12 is disposed over masking layer 11. Masking layer 13 is disposed over insulating layer 12, and has been photolithographically patterned and etched to have via opening V thereat; via opening V defines the location of a via through insulating layer 12, as will become apparent from the following description.
Following the opening of via opening V in masking layer 13, insulating layer 14 is then disposed overall. In similar fashion as before, masking layer 15 is disposed over insulating layer 14, and trench opening T is etched through masking layer 15 at trench location T, which is defined by photolithographically patterned photoresist 16. In this example, however, the patterning of trench opening in photoresist 16 (and thus in mask layer 15) is misaligned relative to via opening V, as shown in FIG. 2a. The misalignment of this example is sufficiently severe that trench opening T does not entirely overlie via opening V in masking layer 13. This is not an uncommon situation, especially as the dimensions of via opening V and trench opening T are pushed to their process limits for this level.
FIG. 2b illustrates the structure following the removal of photoresist 15, after trench opening T is formed in masking layer 15. The structure is then subjected to an etch, removing the exposed portions of insulating layer 14 and insulating layer 12. For minimum size features, this etch is preferably an anisotropic etch that is selective to insulating layers 14, 12 relative to masking layers 15, 13, and to masking layer 11 (serving as an etch stop at the bottom of the via); in this way, trench opening T in masking layer 15 and via opening V in masking layer 13 define the locations at which insulating layers 14, 12, respectively are etched. The resulting structure after this etch is shown in FIG. 2c, which illustrates the good masking performance of the remaining portions of masking layers 13, 15. Masking layer 15, and the exposed portions of masking layer 13 and of masking layer 11 (at the bottom of the via), are then removed by an etch that selectively etches masking layers 13, 15 relative to insulating layers 12, 14, and conductor 10. The completed structure is shown in FIG. 2d. 
As evident from FIG. 2d, the misalignment of trench opening T relative to via opening V causes a narrowing of the via through insulating layer 12. The resulting via through insulating layer 12 in FIG. 2d is evidently narrowed from the patterned via opening V, as evident by the setback of patterned masking layer 13 from this via (along the left edge of the via, in the view of FIG. 2d). This narrowing of the via, resulting from misalignment of the trench and via openings in this conventional process, can result in poor step coverage of the metal to be plated or otherwise deposited into the via, voids in this metal, and poor or open contacts to underlying structure 10.